`timescale 1ns/10ps
module fifo_top_tb();
    reg clk;
    reg rst;
    reg wr_en;
    reg rd_en;
    reg [7:0]data_in;
    wire [7:0]data_out;
    
fifo_syn_top myfifo(.clk(clk),
                    .rst(rst),
                    .wr_en(wr_en),
                    .rd_en(rd_en),
                    .data_in(data_in),
                    .data_out(data_out));
integer i;

always #10 clk=~clk;
initial
  begin
    clk=0;
    rst=0;
    #100 rst=1;
    wr_en=1;
    rd_en=0;
    data_in[7:0]=8'b10101010;
    #20 data_in[7:0]=8'b11001100;
    #20 data_in[7:0]=8'b11111111;
    #20 wr_en=0;
        rd_en=1;
    #120 rd_en=0;

    rst=0;
    #100 rst=1;
    wr_en=1;
    rd_en=0;
     for(i=0;i<16;i=i+1)
      begin
        #20 data_in[7:0]=8'b00000000;
        #20 data_in[7:0]=8'b10101010;
        #20 data_in[7:0]=8'b11001100;
        #20 data_in[7:0]=8'b11111111;    
      end
    #1000 wr_en=0;
    #10 rd_en=1;
    #2000 rst=0; 

  end
  //If you simulate this program in nc of Cadence,you shuld load this"initial"!
  //but if you simulate it in modelsim,it is not needed.  
/*initial
  begin
    $shm_open("fifo_syn.shm");
    $shm_probe("AS");
    #1000 $finish;
  end*/
endmodule  
